The disclosures herein relate generally to ground bounce caused by simultaneous switching of I/O buffers in complex integrated circuits and, more particularly, to a circuit for detecting ground bounce and for reducing data error resulting therefrom.
Simultaneous switching of I/O buffers in complex integrated circuits create sudden shifts in the ground and power plane voltages. These shifts, generically referred to as xe2x80x9cground bounce,xe2x80x9d cause relative shifts in the output buffers"" signals to the extent that a xe2x80x9c0xe2x80x9d can be detected as a xe2x80x9c1xe2x80x9d and vice versa, causing data errors. This problem is becoming increasingly troublesome due to lowered signal voltage levels and their consequent lower noise margins and the increase in density of I/O in increasingly complex chips. The worst ground bounce scenarios occur when most or all I/O buffers drive their output simultaneously.
Prior methods of addressing the above-described problem include adjusting the slew rate of individual I/O buffers, increasing the interplane capacitance using on-chip capacitors, and increasing the decoupling in the immediate region of the transmitting chip. These prior art solutions suggest the use of long phase delay periods on the order of the ground bounce resonance period, but do not include phase de-skewing and are therefore not exceedingly practical without a major revision of bus timing and protocol. They also fail to provide means for detecting ground bounce and for reducing data error.
Therefore, what is needed is a circuit for detecting ground bounce and for reducing data error resulting therefrom.
One embodiment, accordingly, is a circuit for detecting ground bounce and for using this information to reduce data error resulting therefrom. In particular, an on-chip ground bounce detector circuit detects large ground bounce events caused by the simultaneous switching of I/O buffers of the chip and notifies an on-chip logic circuit of the event in one embodiment, the on-chip logic circuit is implemented as a memory interface controller. In this embodiment, the on-chip logic circuit detects a possible ground bounce corrupted write operation to a specific address, issues a special rewrite cycle to that address, and holds the rewritten data valid for one additional clock period to allow the possibly corrupted data to settle prior to its being written, thus ensuring its proper reception at the receiving device.
In another embodiment, the on-chip logic circuit is implemented as a set of counters or shift registers for detecting the number of ground bounce events within a given burst cycle and potentially combining them with their respective addresses and/or data patterns. In this manner, more than one event that may occur during a potentially uninterruptable burst cycle may be detected and an identification may be made as to which of potentially multiple data words need to be corrected.
A principal advantage of the embodiment is that it detects ground bounce events and takes action based on such detection to reduce data error resulting therefrom.